Integrated circuits including clocked digital logic operate with data and control signals. Data signals (or just “data”) are signals that are evaluated by a circuit. Control signals can be used to assert, reset or synchronize functions within an integrated circuit, and can treated as data.
For clocked digital designs, evaluation of control/data signal transitions (from de-asserted to asserted at a rising or falling edge) is done at a clock's active edge (rising or falling). This signal evaluation is referred to as signal capture or latching.
Control/data signals are latched based on setup and hold times in relation to the clock active edge. Setup is the minimum time before a clock active edge that the control/data signal must be stable (unchanging) for it to be predictably latched. Hold is the minimum time after the clock active edge during which data must be stable (unchanging) for it to be predictably latched. Clock setup/hold times depend on circuit design, including operational parameters, such as settling times and signal path timing requirements, and clock/signal frequencies.
With predictable latching based on meeting setup/hold requirements, signal capture can be deterministic. That is, control/data signals can be captured deterministically only if the control/data signal transitions meet the clock setup/hold times. For example, control/data signal transitions that occur within a setup/hold window at an active clock edge cannot be captured deterministically relative to that clock active edge.